Exemplary embodiments of the present invention relate to a semiconductor device design, and more particularly, to a semiconductor integrated circuit (IC) having a chip-on-chip structure.
A wire bonding technology has been used to integrate a control semiconductor IC and a main semiconductor IC into a single package. However, packing semiconductor ICs by wire bonding restricts high speed operations of the semiconductor ICs.
As a way to address this concern, a chip-on-chip package technology is widely used wherein a control semiconductor IC and a main semiconductor IC are stacked in a vertical direction. In other words, the chip-on-chip package technology is a package technology which matches positions of both bump pads between a control semiconductor IC and a main semiconductor IC and directly connects both bump pads without wires. Such a chip-on-chip package technology increases an operating frequency due to high-speed signal transmission, reduces total power consumption, and minimizes an entire chip area.
However, when the chip-on-chip package technology is applied, the bump pad size of the semiconductor IC is too small (e.g., 30-μm×30-μm) to perform a probe test on the bump pads in a test mode. Therefore, in order to achieve a probe test properly, a separate probe test pad having a size of about 60-μm×60-μm is normally desired.
After a wafer level process, a packaging process is performed on the chip-on-chip semiconductor IC in order to use it as a single item. At this time, the IC may be damaged if static electricity is introduced through a pin of the packaged IC. For example, when a person touches a pin of a packaged IC with his/her hands or a test device (e.g., a probe tip for a probe test), a small amount of charges (Q) may be transferred through the IC pin to a bump pad or a probe test pad provided inside the IC. Sine the IC pin has a very small capacitance Cin, a voltage (V) of static electricity transferred through the IC pin can be higher than 1,000 V based on the relation that V=Q/Cin.
Consequently, there is a need for IC designs which can protect ICs from static electricity introduced through a bump pad and a probe test pad provided inside the ICs.